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IIIT Hyderabad LEEE — DLD Preparation

IIIT Hyderabad LEEE — DLD Preparation

About the IIIT Hyderabad LEEE

The LEEE (Lateral Entry Entrance Examination) is conducted by IIIT Hyderabad for admission to the 3rd year (5th semester) of their B.Tech programme. It tests core CS subjects at an undergraduate level.

Key facts:

Note: LEEE is different from semester exams. Semester exams test detailed derivations and circuit design. LEEE tests speed, accuracy, and conceptual clarity through MCQs. You need to prepare both ways.

LEEE DLD Syllabus & Weightage

Based on past LEEE papers and the official syllabus outline, DLD questions in LEEE focus on:

Topic Approx. Questions Difficulty
Number Systems & Conversions 1–2 Easy–Medium
1’s/2’s Complement, Binary Arithmetic 2–3 Medium
Boolean Simplification (Algebraic) 1–2 Medium
K-Map Simplification 2–3 Medium–Hard
Canonical Forms (SOP/POS, minterms) 1–2 Easy–Medium
Combinational Circuits (Adder, MUX, Decoder) 2–4 Medium–Hard
Gate counting / Universal gates 1–2 Easy–Medium

LEEE high-ROI topics for DLD: K-Map simplification, MUX-based function implementation, 2’s complement arithmetic, gate counting, and Boolean identities. These appear almost every year.

Key Differences: Semester Exam vs LEEE

Aspect Semester Exam LEEE
Format Subjective (long answer, derivation, circuit diagrams) Objective MCQs
Time per question 10–20 min ~1 min
What’s tested Step-by-step proofs, complete designs, truth tables Conceptual understanding, shortcuts, traps
Negative marking Usually none Yes — penalizes guessing
Circuit drawing Required Not possible in MCQ — test understanding instead
Typical traps Incomplete simplification Wrong complement, off-by-one in K-Map grouping, BCD overflow confusion

Bottom line: For semester exams, practice writing complete solutions. For LEEE, practice speed + accuracy on MCQs and learn the common traps below.

LEEE-Style MCQs — Unit I Topics

MCQ 1. The 2’s complement of the 8-bit number 01010101 is:
(a) 10101010
(b) 10101011
(c) 10101100
(d) 01010110

Answer & Explanation **Answer: (b) `10101011`** 1's complement of `01010101` = `10101010` Add 1: `10101010 + 1 = 10101011` *Shortcut: Copy bits from right up to and including the first 1, flip the rest.* `01010101` → keep `1` → `_______1` → keep `0` → `______01` → keep `1` → `_____101` → flip rest → `10101011` ✓

MCQ 2. The decimal equivalent of the signed binary number 11001010 in 2’s complement representation is:
(a) −54
(b) −56
(c) −52
(d) +202

Answer & Explanation **Answer: (a) −54** MSB is 1 → negative number. 2's complement of `11001010`: 1's comp = `00110101`, add 1 = `00110110` = 32+16+4+2 = 54 So the number = **−54** *Trap: Option (d) is what you'd get if you treated it as unsigned. Always check whether the question says "signed" or "unsigned".*

MCQ 3. How many 1s are in the binary representation of $(CAB)_{16}$?
(a) 7
(b) 8
(c) 6
(d) 9

Answer & Explanation **Answer: (a) 7** $C = 1100$, $A = 1010$, $B = 1011$ $$(CAB)_{16} = 1100\ 1010\ 1011$$ Count 1s: 2 + 2 + 3 = **7**

MCQ 4. The simplified Boolean expression for $F(A,B,C) = \sum m(0, 2, 4, 5, 6)$ is:
(a) $\overline{C} + A\overline{B}$
(b) $\overline{B} + A\overline{C}$
(c) $\overline{C} + AB$
(d) $A + \overline{C}$

Answer & Explanation **Answer: (a) $\overline{C} + A\overline{B}$** K-Map (3 variable): | | $\overline{B}\overline{C}$ | $\overline{B}C$ | $BC$ | $B\overline{C}$ | |--|--|--|--|--| | $A=0$ | 1 | 0 | 0 | 1 | | $A=1$ | 1 | 1 | 0 | 1 | Group 1: $m_0, m_2, m_4, m_6$ (all $\overline{C}$) → $\overline{C}$ Group 2: $m_4, m_5$ → $A\overline{B}$ $F = \overline{C} + A\overline{B}$

MCQ 5. The minimum number of 2-input NAND gates needed to implement $F = A \oplus B$ is:
(a) 3
(b) 4
(c) 5
(d) 6

Answer & Explanation **Answer: (b) 4** $A \oplus B = A\overline{B} + \overline{A}B$ Using NAND gates: Gate 1: $\overline{AB}$ = NAND(A,B) Gate 2: $\overline{A \cdot \overline{AB}}$ = NAND(A, output of G1) Gate 3: $\overline{B \cdot \overline{AB}}$ = NAND(B, output of G1) Gate 4: NAND(output of G2, output of G3) = $A\overline{B} + \overline{A}B$ ✓ **4 NAND gates.** This is a classic LEEE/GATE question.

MCQ 6. If $F(A,B,C,D) = \sum m(0,1,5,7,8,9,10,14,15)$, the number of essential prime implicants is:
(a) 2
(b) 3
(c) 4
(d) 5

Answer & Explanation **Answer: (c) 4** Draw the 4-variable K-Map and identify prime implicants. A prime implicant is **essential** if it is the only prime implicant covering a particular minterm. Map it out carefully — the 4 essential PIs cover the minterms that no other group can reach. *This is the type of K-Map question LEEE loves — not asking for the expression, but for counts (PIs, essential PIs, literals).*

MCQ 7. The Boolean expression $\overline{(A+B)(\overline{A}+B)}$ simplifies to:
(a) $A$
(b) $\overline{B}$
(c) $A + \overline{B}$
(d) $\overline{A} + \overline{B}$

Answer & Explanation **Answer: (b) $\overline{B}$** $(A+B)(\overline{A}+B)$ $= A\overline{A} + AB + B\overline{A} + BB$ $= 0 + AB + \overline{A}B + B$ $= B(A + \overline{A} + 1) = B$ So $\overline{(A+B)(\overline{A}+B)} = \overline{B}$ *Shortcut: $(A+B)(\overline{A}+B) = B + A\overline{A} = B$ by the distributive/consensus property.*

MCQ 8. In an 8-bit 2’s complement system, the result of adding 01111111 and 00000001 is:
(a) 10000000, which represents +128
(b) 10000000, which represents −128 (overflow)
(c) 00000000, which represents 0
(d) The operation is undefined

Answer & Explanation **Answer: (b) `10000000`, which represents −128 (overflow)** `01111111` = +127, `00000001` = +1 Sum = `10000000` = −128 in 2's complement **Overflow** occurred because two positive numbers produced a negative result. The carry into the MSB (1) ≠ carry out of the MSB (0). *LEEE frequently tests overflow detection — memorize the rule.*

MCQ 9. The Gray code for decimal 13 is:
(a) 1011
(b) 1010
(c) 1110
(d) 1111

Answer & Explanation **Answer: (a) 1011** Decimal 13 = Binary `1101` $G_3 = B_3 = 1$ $G_2 = B_3 \oplus B_2 = 1 \oplus 1 = 0$ $G_1 = B_2 \oplus B_1 = 1 \oplus 0 = 1$ $G_0 = B_1 \oplus B_0 = 0 \oplus 1 = 1$ Gray = **1011**

MCQ 10. How many valid BCD numbers can be represented using 12 bits?
(a) 999
(b) 1000
(c) 4096
(d) 1024

Answer & Explanation **Answer: (b) 1000** 12 bits = 3 BCD digits. Each BCD digit: 0–9 → 10 values. Total valid combinations = $10 \times 10 \times 10 = 1000$ (000 to 999) *Trap: (c) 4096 = $2^{12}$ is the number of 12-bit binary combinations, not valid BCD. (d) 1024 = $2^{10}$ is also a distractor.*

LEEE-Style MCQs — Unit II Topics

MCQ 11. A 4:1 MUX with select inputs $S_1 = A$, $S_0 = B$ and data inputs $I_0 = C$, $I_1 = \overline{C}$, $I_2 = 0$, $I_3 = 1$ implements the function:
(a) $\sum m(1, 2, 6, 7)$
(b) $\sum m(1, 3, 6, 7)$
(c) $\sum m(0, 2, 6, 7)$
(d) $\sum m(1, 2, 3, 6, 7)$

Answer & Explanation **Answer: (a) $\sum m(1, 2, 6, 7)$** Expand each MUX input: - $S_1S_0 = 00$ → $Y = C = \overline{A}\overline{B}C$ → minterm 1 - $S_1S_0 = 01$ → $Y = \overline{C} = \overline{A}B\overline{C}$ → minterm 2 - $S_1S_0 = 10$ → $Y = 0$ → no minterms - $S_1S_0 = 11$ → $Y = 1 = AB\overline{C} + ABC$ → minterms 6, 7 $F = \sum m(1, 2, 6, 7)$

MCQ 12. The minimum number of 2-input AND and OR gates (not counting NOT gates) needed to implement a Full Adder Sum output is:
(a) 2 AND + 1 OR
(b) 3 AND + 2 OR
(c) Not possible with AND/OR/NOT alone without XOR
(d) 4 AND + 3 OR

Answer & Explanation **Answer: (d) 4 AND + 3 OR** $S = A \oplus B \oplus C_{in}$ $= A\overline{B}\overline{C} + \overline{A}B\overline{C} + \overline{A}\overline{B}C + ABC$ This is a 4-minterm SOP → 4 AND gates (3-input each, but 2-input can be cascaded) and 1 OR gate for the top level. When strictly using 2-input gates, you need 4 three-input AND terms (each needing 2 two-input ANDs = 8, but with shared NOTs and restructuring → **4 AND + 3 OR** in the optimal decomposition). The real takeaway: XOR gates drastically reduce complexity.

MCQ 13. A 3:8 decoder with an enable input can function as a:
(a) 8:3 encoder
(b) 1:8 demultiplexer
(c) 8:1 multiplexer
(d) 3-bit comparator

Answer & Explanation **Answer: (b) 1:8 demultiplexer** When the **enable** line is used as the **data input**, the decoder routes that data to one of 8 outputs based on the 3 select lines — exactly the behavior of a 1:8 DEMUX. *This is a very frequently asked conceptual MCQ in LEEE and GATE.*

MCQ 14. The output of a Half Adder for inputs $A=1$, $B=1$ is:
(a) Sum = 1, Carry = 0
(b) Sum = 0, Carry = 1
(c) Sum = 1, Carry = 1
(d) Sum = 0, Carry = 0

Answer & Explanation **Answer: (b) Sum = 0, Carry = 1** $S = A \oplus B = 1 \oplus 1 = 0$ $C = A \cdot B = 1 \cdot 1 = 1$ *Seems easy, but under time pressure candidates confuse XOR with OR.*

MCQ 15. How many Full Adders are needed to add two 16-bit numbers?
(a) 15
(b) 16
(c) 17
(d) 32

Answer & Explanation **Answer: (b) 16** An $n$-bit ripple carry adder uses exactly **$n$ full adders** (the LSB full adder gets $C_{in} = 0$). Some textbooks use 1 half adder + 15 full adders, but the standard answer for "full adders needed" is **16** (a half adder is a special case of a full adder with $C_{in}$ tied to 0).

MCQ 16. A BCD adder produces the binary sum $10010$ (decimal 18). The corrected BCD output is:
(a) 0001 1000
(b) 0001 0010
(c) 0010 1000
(d) 0001 1001

Answer & Explanation **Answer: (a) 0001 1000** Binary sum = `10010` = 18. Since the sum > 9, or equivalently carry = 1: Correction: `10010` is actually the 5-bit result; the lower 4 bits `0010` with carry-out 1 means we add 0110: $0010 + 0110 = 1000$ with new carry = 0, but original carry = 1 BCD result: **0001 1000** (1 and 8 → 18) ✓

MCQ 17. The number of select lines in a 32:1 MUX is:
(a) 4
(b) 5
(c) 6
(d) 32

Answer & Explanation **Answer: (b) 5** $2^n = 32 \Rightarrow n = 5$ select lines.

MCQ 18. Which gate is used to check equality of two bits?
(a) AND
(b) OR
(c) XOR
(d) XNOR

Answer & Explanation **Answer: (d) XNOR** XNOR outputs 1 when inputs are **equal**: $A \odot B = \overline{A \oplus B}$. | A | B | XNOR | |---|---|------| | 0 | 0 | 1 | | 0 | 1 | 0 | | 1 | 0 | 0 | | 1 | 1 | 1 | This is why comparators use XNOR gates for the equality check.

MCQ 19. The total number of gates required to build a Full Adder using only 2-input NAND gates is:
(a) 7
(b) 9
(c) 5
(d) 11

Answer & Explanation **Answer: (b) 9** A Full Adder needs 2 XOR + 2 AND + 1 OR. Each XOR = 4 NANDs, each AND = 2 NANDs, each OR = 3 NANDs → far too many. But with **shared gates** and optimized design, a Full Adder can be built with **9 NAND gates**. This is a well-known result.

MCQ 20. A priority encoder has 8 inputs. If inputs $I_7$, $I_5$, and $I_2$ are all HIGH simultaneously, the output code is:
(a) 010
(b) 101
(c) 111
(d) 001

Answer & Explanation **Answer: (c) 111** Priority encoders output the **highest-priority** (highest-numbered) active input. $I_7$ has the highest priority → output = $111_2 = 7$. *A simple encoder would malfunction here (undefined output for multiple active inputs). This is why priority encoders exist.*

LEEE Exam Strategy & Tips

Time Management

  • Digital Logic questions are scoring — they’re formulaic and quick if you know the method. Do them early.
  • Budget ~1 minute per MCQ. If a K-Map question takes > 2 minutes, mark and revisit.
  • Don’t draw full K-Maps on rough paper for every question — learn to visualize 3-variable maps mentally.

Common Traps to Watch For

  1. Signed vs Unsigned — Always check what representation the question uses. 10000000 is 128 (unsigned) but −128 (signed 2’s complement).
  2. BCD vs Binary — \((19)_{BCD} = 00011001 \neq (11001)_2 = 25\).
  3. K-Map wrap-around — Don’t forget that row 0 and row 3 are adjacent, and column 0 and column 3 are adjacent in a 4-variable K-Map.
  4. Don’t-cares — If a K-Map question includes don’t-cares, use them. If you ignore them, you’ll get a valid but non-minimal answer.
  5. MUX implementation — When implementing an $n$-variable function with a $2^{n-1}$:1 MUX, the remaining variable appears as 0, 1, $X$, or $\overline{X}$ at the data inputs — not as a select line.
  6. Gate counting — NAND-only or NOR-only implementations: memorize that XOR = 4 NANDs, Full Adder = 9 NANDs.
  7. Priority encoder output — If no input is active, the output is typically invalid — check the valid bit $V$.

Must-Memorize for LEEE

Item Value
XOR using NAND gates 4 gates
Full Adder using NAND gates 9 gates
$n$-bit ripple carry adder delay $2n$ gate delays (approx)
BCD correction threshold Sum > 9 → add 0110
2’s complement range ($n$ bits) $-2^{n-1}$ to $2^{n-1}-1$
Number of functions of $n$ variables $2^{2^n}$
Minterms for $n$ variables $2^n$
$n$:1 MUX select lines $\log_2 n$
Decoder with enable = Demultiplexer
  1. First pass: Solve all MCQs above without time limit, understand each explanation
  2. Second pass: Time yourself — 1 min per MCQ, strict
  3. Third pass: Do only the ones you got wrong; analyze why you made errors
  4. Mock: Mix DLD MCQs with other LEEE subjects for realistic simulation

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